For example, a trench-gate power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that achieves low on-resistance and high breakdown voltage has been proposed as a conventional silicon carbide semiconductor device (see Patent Document 1 (Japanese Patent Laying-Open No. 9-199724) and Patent Document 2 (Japanese Patent Laying-Open No. 10-247732), for example).
As shown in FIG. 16, for example, this conventional trench-gate power MOSFET is formed of a semiconductor stacked substrate 4 including an n+-type silicon carbide crystal substrate 1, an n−-type silicon carbide crystal layer 2 formed on n+-type silicon carbide crystal substrate 1, a p-type silicon carbide crystal layer 3 formed on n−-type silicon carbide crystal layer 2, and an n+-type source region 5 and a p+-type region 6 formed in a surface of p-type silicon carbide crystal layer 3. A hexagonal silicon carbide crystal is used as a silicon carbide crystal and an upper surface (a principal surface) of semiconductor stacked substrate 4 is a carbon surface of a substantial (0001−) surface.
In this conventional trench-gate power MOSFET, a trench 7 extending from a surface of semiconductor stacked substrate 4 through n+-type source region 5 and p-type silicon carbide crystal layer 3 into n−-type silicon carbide crystal layer 2 is formed. This trench 7 has side surfaces 7a perpendicular to a surface of n−-type silicon carbide crystal layer 2 and a bottom surface 7b parallel to the surface of n−-type silicon carbide crystal layer 2.
A thin film semiconductor layer 8 made from an n-type silicon carbide crystal is epitaxially grown on side surfaces 7a of trench 7, and a gate insulating film 9 is formed on a surface of thin film semiconductor layer 8. A gate electrode layer 10 is formed inside gate insulating film 9. An interlayer insulating film 11 is formed on gate electrode layer 10, and a source electrode layer 12 is formed on n+-type source region 5 and p-type silicon carbide crystal layer 3 as well as on interlayer insulating film 11. A drain electrode layer 13 is formed on a surface of n+-type silicon carbide crystal substrate 1 (a lower surface of semiconductor stacked substrate 4).
In the conventional silicon carbide semiconductor device having such a configuration, the application of an electric field to gate insulating film 9 by the application of a voltage to gate electrode layer 10 causes a storage type channel to be induced at thin film semiconductor layer 8, so that a current flows between source electrode layer 12 and drain electrode layer 13.    Patent Document 1: Japanese Patent Laying-Open No. 9-199724    Patent Document 2: Japanese Patent Laying-Open No. 10-247732